101314 - DIGITAL ELECTRONICS II

Marcos Faúndez Zanuy

T1. Introduction

A brief introduction to digital information and its representation and to digital circuits, purpose-specific processors and the computer (Von Neumann model) as well as machine and assembly language and its relationship with high-level languages ​​(compilation / translation).

T2. Sequential logic circuits

Memory and synchronization needs. Clock signal. Definition of synchronous sequential circuit. Flank-activated bistable D: definition and implementation with two multiplexers, propagation times and timelines. Interconnection rules for constructing valid sequential circuits. Structure of a sequential circuit (Mealy and Moore models). Transition table and output table. State graphs for the Moore model. Simplified timelines.

Logical analysis: from the circuit to the state graph. Synthesis: from the functional specification to the state graph and from the latter to the logic diagram of the circuit with the minimum number of bistables. Temporal analysis: critical paths and minimum cycle times

T3. Special purpose processors

Introduction. Design of purpose-specific processors with a process unit (which processes n-bit words) and a control unit (which generates the control word in each cycle). The process unit is designed adhoc using n-bit combinational and sequential blocks. The control unit is specified using a Moore state graph. Examples with synchronous data input and output: add four numbers, calculate the MCD of two numbers with the Euclidean algorithm, etc. Asynchronous communication protocol for data input and output: Four-phase handshaking. Examples with asynchronous input and output.

T4. General process unit

Introduction: from specific purpose processors to general purpose processor. Log bank with two reading buses and one writing bus. Arithmetic-logic unit with functionality of bitwise logical operations, arithmetic operations (addition, subtraction and multiplications and divisions by powers of two for natural and integers), comparisons (equal and less and less than or equal to natural and integers) and movement. Structure of the General Process Unit (UPG). Connected between the UPG and the Control Unit: control word and zero condition bit.

Actions to be performed in one of these problems using the UPG. Mnemonics of actions (AND, OR, XOR, NOT, ADD, SUB, SHA, SHL, CMPLT, CMPLE, CMPEQ, CMPLTU, CMPLE, MOV, IN, OUT and NOP) and bits of the associated control word. Shares with immediate values ​​and shares that do not modify any record. Design of purpose-specific processors using the UPG (control unit specification using a state graph and the control word using mnemonics). Input / output address space and IN and OUT actions.

Asynchronous data input and output using the four-phase handshaking protocol. Design examples from a code in a high-level language that specifies the functionality of the processor (adder of four numbers, calculation of the MCD by the Euclidean algorithm, etc.).

T5. General control unit

Initial implementation of the control unit (like any other sequential circuit): with a state register, a ROM memory (where in each word the following two possible states are stored, according to the bit of condition z, and the word of control that will govern the UPG during a cycle) and a bus multiplexer to select the next state according to z. Computer model Von Neumann and Harvard. Instruction memory in ROM. From the graph of states to the program in machine / assembler language. Definitive control unit structure with implicit sequencing, 16-bit instructions, and instruction decoder for obtaining the 50-bit control word from the 16-bit instruction. Format (instructions of 1, 2 or 3 records) and coding of SISA instructions. Types of use: arithmetic-logic and comparison, sequence break, input-output, motion (loading a register with a constant) and adding a small constant. Examples of passing from graphs (specifying a UC with specific objectives that together with the UPG execute an algorithm) to code fragments in SISA assembly language to perform the same function (although it usually requires more cycles).

T6. Memory and output

RAM, simple operating model (read and write schedules, access time for a read and set-up, and pulse width of the write permission signal for a write). Memory address space. Connected from data memory to processor. Read (load, LD) and write (store, ST) instructions: semantics, format in machine language and syntax in assembler. Examples of modifying the state of the computer for specific load and store instructions. Examples of small programs with memory access.

Simple input / output subsystem consisting of a keyboard and a printer with side effect of resetting the status register (port) when reading (keyboard) or writing (printer) the data register. Input / output with survey synchronization. Examples of small programs with data input and output.

T7. Machine and assembler language

General review of machine language and SISA assembler (25 instructions) that has been defined in the two previous topics. Exercises on: a) assembling and disassembling SISA code, b) how the state of the computer is modified after executing an instruction or a small program and c) writing small programs in assembly language.

T8. Unicycle processor

Complete some details of the unicycle implementation (SISC Harvard unicycle) of the processor that runs programs in SISA machine language that was already being created in topics 8, 9 and 10: a) small modification of the ALU of the UPG to run the movement instructions immediately to the 8 bits heaviest of a MOVHI register, b) a single address bus for the input and output space and c) design of the instruction decoder (to obtain the word 46-bit control from the 16-bit instruction) using a small ROM and some multiplexers and ports. Contents of the instruction decoder ROM.

Temporary restrictions on write permission signals in memory and data input / output. Examples of design modification of the SISC Harvard unicycle so that you can execute, in addition to the original 25 instructions, some other new instructions. Calculation of the critical path of the unicycle computer and minimum cycle time. Execution time of small programs.

T9. Multicycle processor

Justification for multicycle implementation (SISC Harvard multicycle) versus unicycle (SISC Harvard unicycle). Modifications to the processor control unit. Design of the sequential control unit: state graph and implementation. Temporary restrictions on write permission signals in memory and data input / output. Examples of modifying the design of the SISC Harvard multicycle so that you can execute, in addition to the original 25 instructions, some other new instructions. Calculation of the critical path of the multicycle computer and minimum cycle time. Execution time of small programs.