TecnoCampus Foundation
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General information

Subject type: Mandatory

Coordinator: Joan Triadó Aymerich

Trimester: Second term

Credits: 4

Teaching staff: 

Marcos Faúndez Zanuy
Eduard Ros Rodríguez 
Ferran Mercader Álvarez 

Teaching languages

  • Catalan

Some questions in the moodle questionnaires are in Catalan, the rest in Spanish

Skills

Specific skills

  • CE11: Knowledge of the basics of electronics.

Description

Introduction to Digital Electronics with discrete components (logic gates and combinational, arithmetic and sequential integrated circuits). The theory is oriented towards the practical assembly of digital circuits. The elementary concepts of binary arithmetic are also explained, and you learn to synthesize and analyze circuits that solve simple tasks.

Contents

1. Logical functions.

Description

Introduction
A brief introduction to digital information and its representation and to digital circuits, purpose-specific processors and the computer (Von Neumann model) as well as machine and assembly language and its relationship with high-level languages ​​(compilation / translation).

Representation of natural numbers
Representation of natural numbers in decimal and binary and their generalization to the conventional system in base b. Hexadecimal Range of representation. Range extension algorithm. Basic changes between conventional systems.

Related activities

First partial test.

Exercise resolution.

Laboratory practices.

 

2. Combinational circuits.

Description

Combinational logic circuits
Definition of combinational logic circuit. Schedules Logical variables and functions. truth table Not, And and Or logic gates. Logic diagram of a circuit. Interconnection rules to build valid combinational logic circuits. Logical analysis (from schema to truth table). Synthesis (from the functional description to the truth table and from the latter to the logic circuit): in sum of minterms, with a decoder and Or gates, with a ROM memory and minimal synthesis in product of sums using Karnaugh maps. Time analysis (schedules and propagation time from an input to an output).

Related activities

First partial test.

Exercise resolution.

Laboratory practices.

 

3. Arithmetic circuits.

Description

Combinational arithmetic blocks for natural numbers:
Arithmetic algorithms for addition, subtraction and multiplication and division by powers of two natural numbers represented in binary. Full-adder, Half¿adder and Full-sudstractor. Combinational blocks that implement the above arithmetic algorithms with detection of result not representable in n bits. Comparators of equal, less and less than or equal to. Non-arithmetic combinational blocks (bit-by-bit logical operators, design of tree multiplexers). Design of new arithmetic blocks.

Integers: Representation and Combinational Arithmetic Blocks:
Representation of integers. two's complement Range and range extension algorithm. Change representation for integers between sign and magnitude in decimal and two's complement. Arithmetic algorithms and combinational blocks that implement them (with detection of a result not representable in n bits): addition, change of sign, subtraction, multiplication and division by powers of two and comparators of less than and less than or equal to. Adder/subtractor with result detection not representable by natural numbers and integers.

Related activities

Second partial test.

Exercise resolution.

Laboratory practices.

 

4. Sequential circuits.

Description

Memory and synchronization requirements. clock signal Definition of synchronous sequential circuit. The edge-triggered D bistable: definition and implementation with two multiplexers, propagation times and timings. Interconnection rules for building valid sequential circuits. Structure of a sequential circuit (Mealy and Moore models). Table of transitions and table of outputs. State graphs for Moore's model. Simplified schedules. Logical analysis: from the circuit to the state graph. Synthesis: from the functional specification to the state graph and from the latter to the logic diagram of the circuit with the minimum number of bistables. Time analysis: critical paths and minimum cycle time.

Related activities

Second partial test.

Exercise resolution.

 

5. Programmable circuits.

Description

SPLD, PAL, GAL, CPLD, FPGA.

Door arrays, interconnections, input / output.

Programming technologies. Fuse, antifuse, EPROM, SRAM.

Programming process. VHDL.

Contour exploration logic.

Related activities

Second partial test.

 

Evaluation system

The final grade will be the weighted average of the grades of the assessable activities:

First partial test: 35%

Second partial test: 35%

Laboratory practices: 30%

Recovery exam: 70%

There will be a first partial test in the middle of the course and a second partial test at the end of the course.

For students who do not pass the assessment during the course, 30% of the internship grade will be maintained, and an overall retake exam will be held which will be worth 70% of the grade.

The resit exam may be used to pass the subject with a final grade of 5, but not to obtain a grade higher than 5.

Practice activities are not recoverable.

REFERENCES

Basic

Thomas Floyd. Fundamentals of digital systems. Pearson, 2006. ISBN 9788483220856.

Complementary

Daniel Gajski. Principles of digital design. Prentice Hall, 1997. ISBN 84-8322-004-0.

John Hayes. Introduction to digital logical design. Addison-Wesley, 1996. ISBN 0-201-62590-3.