DIGITAL ELECTRONICS II TecnoCampus | Centers attached to Pompeu Fabra University and Business Park

General information

Subject type: Mandatory

Coordinator: Julián Horrillo Tello

Trimester: First term

Credits: 4

Teaching staff:

Marcos Faúndez Zanuy

Teaching languages

Some questions in the moodle questionnaires are in Catalan, the rest in Spanish

Skills

Specific skills

CE21: Understand the basics and applications of digital electronics and microprocessors.
CE24: Train to design analog, digital and power electronic systems.

Description

This subject is the continuation of digital electronics I. While in digital electronics I the constituent blocks of digital systems are explained and we learn to synthesize and analyze circuits that solve simple tasks, in this course the construction of a simple programmable processor in assembly language.

The continuation of the subject of digital electronics II is the subject of microprocessors, where basically it will work on a micro-controller ARM cortex M4.

This subject has methodological and digital resources to make possible its continuity in non-contact mode in the case of being necessary for reasons related to the Covid-19. In this way, the achievement of the same knowledge and skills that are specified in this teaching plan will be ensured.

The Tecnocampus will make available to teachers and students the digital tools needed to carry out the course, as well as guides and recommendations that facilitate adaptation to the non-contact mode.

Learning outcomes

1. Implement hardware using discrete digital components (SSI, MSI), programmable (PLD), microprocessors, microcontrollers and DSP. (CE21, CE28)

2. Design algorithms and write code in high and low level programs. (CE23)

3. Apply programming tools for PLD devices, microprocessors, microcontrollers and DSP of digital equipment. (CE21)

4. Critically select the appropriate components for each application, interpreting and analyzing their characteristics. (CE24)

5. Handles the scientific-technical terminology of digital electronic components in English. (CE21, CE24, CE28)

6. Prepares technical project reports, evaluates alternatives and justifies their analyzes and design criteria(CE21, CE24, CE28)

At the end of the course the student must be able to:

Explain in your own words the operation of a Von Neuman type computer: its internal structure at the level of the processor, bus, memory and input / output subsystems and the execution of a program in machine language. Also explain the most relevant differences between the machine language of RISC and CISC computers.
Explain what a sequential logic circuit is (Mealy's general case and Moore's particular case). Specify the operation of a skinny activated bistable D and its internal logic diagram using two multiplexers.
Analyze small Moore sequential circuits (obtain their state graph and their minimum cycle time, as well as draw simplified timelines of their operation).
Synthesize (with the least number of flank-activated D flip-flops and any of the techniques studied in combinational circuit synthesis) small Moore sequential circuits.
Explain the four-step asynchronous communication protocol (Four-Phase Handshaking) and apply it to data input and output in specific purpose processors.
Draw the interconnection structure of the general process unit (UPG) at the block level and the internal logical scheme of each block that makes it up (register bank and logical arithmetic unit).
Draw the Moore state graph of the specific purpose control unit so that, together with the general process unit (UPG), it implements a specific functionality.
Explain the steps required to transform a specific purpose control unit (implementation of a state graph) into a general purpose control unit (UCG) which, together with the general process unit (UPG), will form a processor Simple RISK. Justify and explain implicit sequencing and coding of instructions.
Justify the need for a large data memory. Explain the operation of a block of RAM using a timeline of its input and output signals (simplified model).
Draw the internal logic diagram of a simple input / output subsystem with a keyboard and a printer.
Draw the interconnection scheme of the memory subsystems

Working methodology

The teaching method of the subject follows what has been called in the ICE of the UPC as Pygmalion method, which can be summarized in the following points:

1. An ambitious end goal. Students go from knowing basic digital circuits to how a computer is built inside to designing in detail a computer that consists of about 3.000 logic gates. This is an important motivating element.

2. A detailed program of activities: what students should do in class and especially outside of class. After each two-hour class of theory and problems they should study 1,5 hours and solve a collection of exercises that will take them approximately 1,5 hours (these exercises are electronic delivery Moodle questionnaires and can be others more complex on paper delivery) and to be delivered at the beginning of the next class.

3. The program of activities has affordable steps and, little by little, the objectives of the subject are achieved (the ambitious end motivates and the affordable steps make the path viable).

4. The result of each activity of the program materializes in a delivery, that shows if the student has done the task. The solutions of the exercises and problems are given and also the quality criteria are given to evaluate them.

5. Timely feedback mechanisms (based on course deliveries) to let the student know how it is going (and the teacher too): 1) Students can know immediately if each question in the Moodle quiz they have solved is right or wrong and they can answer as many times as they want until they answer correctly. 2) At the beginning of each class, doubts about the Moodle exercises are clarified and, if necessary, the paper delivery problems they have done at home are corrected, knowing if they have done it right or wrong. 3) In each class, if applicable, the student will have to solve exercises individually or in groups that will indicate how it goes. 4) There are three theory and problem exams / tests and four laboratory tests distributed throughout the course, which also give timely feedback.

6. Specific actions are prepared for students who have more difficulties (and also for the most advanced): private consultations, workshops for problem solving, etc.

7. Cooperative learning techniques are used to motivate students to perform the activities. In theory and problem classes, active learning techniques are used to make the teacher's presentations short and for students to work in class as well.

8. The grading method is one more stimulus to walk the path, to do the activities on time, and therefore to learn.

9. There is a plan for the systematic collection of data on the evolution of the course, and this data is used as the engine of a process of continuous improvement.

Memory and synchronization needs. Clock signal. Definition of synchronous sequential circuit. Flank-activated bistable D: definition and implementation with two multiplexers, propagation times and timelines. Interconnection rules for constructing valid sequential circuits. Structure of a sequential circuit (Mealy and Moore models). Transition table and output table. State graphs for the Moore model. Simplified timelines.

Logical analysis: from the circuit to the state graph. Synthesis: from the functional specification to the state graph and from the latter to the logic diagram of the circuit with the minimum number of bistables. Temporal analysis: critical paths and minimum cycle times

T3. Special purpose processors

Introduction. Design of purpose-specific processors with a process unit (which processes n-bit words) and a control unit (which generates the control word in each cycle). The process unit is designed adhoc using n-bit combinational and sequential blocks. The control unit is specified using a Moore state graph. Examples with synchronous data input and output: add four numbers, calculate the MCD of two numbers with the Euclidean algorithm, etc. Asynchronous communication protocol for data input and output: Four-phase handshaking. Examples with asynchronous input and output.

T4. General process unit

Introduction: from specific purpose processors to general purpose processor. Log bank with two reading buses and one writing bus. Arithmetic-logic unit with functionality of bitwise logical operations, arithmetic operations (addition, subtraction and multiplications and divisions by powers of two for natural and integers), comparisons (equal and less and less than or equal to natural and integers) and movement. Structure of the General Process Unit (UPG). Connected between the UPG and the Control Unit: control word and zero condition bit.

Actions to be performed in one of these problems using the UPG. Mnemonics of actions (AND, OR, XOR, NOT, ADD, SUB, SHA, SHL, CMPLT, CMPLE, CMPEQ, CMPLTU, CMPLE, MOV, IN, OUT and NOP) and bits of the associated control word. Shares with immediate values and shares that do not modify any record. Design of purpose-specific processors using the UPG (control unit specification using a state graph and the control word using mnemonics). Input / output address space and IN and OUT actions.

Asynchronous data input and output using the four-phase handshaking protocol. Design examples from a code in a high-level language that specifies the functionality of the processor (adder of four numbers, calculation of the MCD by the Euclidean algorithm, etc.).

T5. General control unit

Initial implementation of the control unit (like any other sequential circuit): with a state register, a ROM memory (where in each word the following two possible states are stored, according to the bit of condition z, and the word of control that will govern the UPG during a cycle) and a bus multiplexer to select the next state according to z. Computer model Von Neumann and Harvard. Instruction memory in ROM. From the graph of states to the program in machine / assembler language. Definitive control unit structure with implicit sequencing, 16-bit instructions, and instruction decoder for obtaining the 50-bit control word from the 16-bit instruction. Format (instructions of 1, 2 or 3 records) and coding of SISA instructions. Types of use: arithmetic-logic and comparison, sequence break, input-output, motion (loading a register with a constant) and adding a small constant. Examples of passing from graphs (specifying a UC with specific objectives that together with the UPG execute an algorithm) to code fragments in SISA assembly language to perform the same function (although it usually requires more cycles).

T6. Memory and output

RAM, simple operating model (read and write schedules, access time for a read and set-up, and pulse width of the write permission signal for a write). Memory address space. Connected from data memory to processor. Read (load, LD) and write (store, ST) instructions: semantics, format in machine language and syntax in assembler. Examples of modifying the state of the computer for specific load and store instructions. Examples of small programs with memory access.

Simple input / output subsystem consisting of a keyboard and a printer with side effect of resetting the status register (port) when reading (keyboard) or writing (printer) the data register. Input / output with survey synchronization. Examples of small programs with data input and output.

T7. Machine and assembler language

General review of machine language and SISA assembler (25 instructions) that has been defined in the two previous topics. Exercises on: a) assembling and disassembling SISA code, b) how the state of the computer is modified after executing an instruction or a small program and c) writing small programs in assembly language.

T8. Unicycle processor

Complete some details of the unicycle implementation (SISC Harvard unicycle) of the processor that runs programs in SISA machine language that was already being created in topics 8, 9 and 10: a) small modification of the ALU of the UPG to run the movement instructions immediately to the 8 bits heaviest of a MOVHI register, b) a single address bus for the input and output space and c) design of the instruction decoder (to obtain the word 46-bit control from the 16-bit instruction) using a small ROM and some multiplexers and ports. Contents of the instruction decoder ROM.

Temporary restrictions on write permission signals in memory and data input / output. Examples of design modification of the SISC Harvard unicycle so that you can execute, in addition to the original 25 instructions, some other new instructions. Calculation of the critical path of the unicycle computer and minimum cycle time. Execution time of small programs.

T9. Multicycle processor

Justification for multicycle implementation (SISC Harvard multicycle) versus unicycle (SISC Harvard unicycle). Modifications to the processor control unit. Design of the sequential control unit: state graph and implementation. Temporary restrictions on write permission signals in memory and data input / output. Examples of modifying the design of the SISC Harvard multicycle so that you can execute, in addition to the original 25 instructions, some other new instructions. Calculation of the critical path of the multicycle computer and minimum cycle time. Execution time of small programs.

Learning activities

		Dedication
		Hours	Percentage
Guided learning	Large group / theory	30	30%
	Medium group / internships	0
	Small group / laboratory	10	10%
	Directed activities	0
Autonomous learning		60	60%

T1: Introduction T2: Sequential logic circuits		Dedication: 10 h	Large group / Theory: 4h Directed activities: h Autonomous learning: 6am
Description	Introduction. Introduction to sequential logic circuits: the general case of Mealy and the particular case of Moore. Analysis and synthesis of Moore sequential circuits with the minimum number of D flip-flops activated per flank. Calculation of the minimum cycle time of a circuit.
Related activities	Topic exercises ET2a, ET2b, ET2c
Links to learning outcomes	Links to learning outcomes 2 to 4, competence E21

T3: Purpose-specific processors		Dedication: 10 h	Large group / Theory: 4 Directed activities: Autonomous learning: 6am
Description	Design of purpose-specific processors with a process unit (which processes n-bit words) and a control unit (which generates the control word in each cycle). Examples with synchronous data input and output. Asynchronous communication protocol for data input and output (four-phase handshaking).
Related activities	ET3a, ET3b
Links to learning outcomes	Links with learning outcomes 5, 7 and 8: CB3, E21 and E24 competences

Exam 1: Topics 1 to 3		Dedication: 3h	Exam duration: 1h Autonomous learning: 2am
Description	Examination of topics 1 to 3
Related activities	ET2a, ET2b, ET2c (optional), ET3a, ET3b
Links to learning outcomes	Links to learning outcomes 2, 4, 5, 7 and 8

T4: General process unit (UPG)		Dedication: 15h	Large group / Theory: 6h Directed activities: Autonomous learning: 9am
Description	Notion of general purpose processor Introduction to the block-level structure of the general process unit (UPG) and the internal logic circuit of the blocks that make it up: register bank and logical arithmetic unit. Design of the specific purpose control unit so that together with the general process unit they implement a given functionality
Related activities	ET 4a, ET4b, ET4c
Links to learning outcomes	Links to learning outcomes 6, competence E24

T5: General control unit: from the graph of states to the program		Dedication: 10h	Large group / Theory: 4h Autonomous learning: 6am
Description	Introduction to implicit sequencing and coding of instructions using a compact format
Related activities	ET5a, ET5b
Links to learning outcomes	Links to learning outcomes 8, competence CB3 and E24

T6: Input / output and memory		Dedication: 5h	Large group / Theory: 2h Directed activities: Autonomous learning: 3am
Description	Understanding the interconnection structure of the input / output subsystems and data memory connected to the general process unit. Description of the internal logic diagram of the input / output subsystem with a keyboard and a printer and the blocks that make it up. Design of the specific purpose control unit so that together with the general process unit and the input / output and memory subsystems implement a given functionality
Related activities	ET6b topic exercises (ET6a optional)
Links to learning outcomes	Links to learning outcomes 9 to 11, competence E24

Exam 2: Topics 4 to 6		Dedication: 3h	Exam duration: 1h Autonomous learning: 2am
Description	Examination of topics 4 to 6
Related activities	ET4a, ET4b, ET4c, ET4a, ET4b, ET5a, ET5b, ET6
Links to learning outcomes	Links to learning outcomes 1 to 11

T7: The SISA-I machine and assembly language		Dedication: 5h	Large group / Theory: 2h Directed activities: Autonomous learning: 3am
Description	Introduction to the SISA-I machine language instruction set and the specification of its assembly language
Related activities	ET7 topic exercises
Links to learning outcomes	Links to learning outcomes 1, competence CB3 and E24

T8: SISP-I-1 unicycle processor		Dedication: 10h	Large group / Theory: 4h Directed activities: Autonomous learning: 6am
Description	Understanding the internal structure and operation of the SISP-I-1 processor where each instruction is executed in a single cycle.
Related activities	Topic exercises ET8a, ET8b
Links to learning outcomes	Links to learning outcomes 1, CB3 and E24 competence

T9: SISP-2 multi-cycle processor		Dedication: 3h	Large group / Theory: 1h Directed activities: Autonomous learning: 2am
Description	Understanding the internal structure and operation of the SISP-2 processor where there are slow (read / write to memory) and fast instructions.
Related activities	ET9 topic exercises
Links to learning outcomes	Links to learning outcomes 1, CB3 and E24 competence

Exam 3: Topics 7 to 9		Dedication: 3h	Exam duration: 1h Autonomous learning: 2am
Description	Examination of topics 11 to 12
Related activities	ET11, ET12a, ET12b
Links to learning outcomes	Links to learning outcomes 1 to 11

Laboratory sessions

Practice 1: Sequential circuits		Dedication: 8h	Large group / Theory: Guided activities: 4h Autonomous learning: 4am
General description	Design a sequential digital system, applying the systematics resolution of finite automata following the Moore model. Implementation with bistables and doors / ROM Know how to interpret a state transition diagram. Experiment with a logic circuit simulator
Support material	Orcad Pspice Simulator
Deliverable and links to the evaluation	Pre-test. If applicable, circuit simulation file. No final report is required. The final grade is based on oral questions
Specific objectives	At the end of the activity the student must be able to: Design and simulate a sequential digital logic circuit
Links to learning outcomes	Links to learning outcomes 2 to 4 and 11, CB3 and E24 competence

Practice 2: installation and commissioning development environment Keil uVISION and CORTEX ARM M4		Dedication: 4h	Large group / Theory: Directed activities: 2 Autonomous learning: 2am
General description	System installation and configuration.
Support material	uVISION, TIVA TM4C123G launchpad development board
Deliverable and links to the evaluation	Pre-test. Demonstration of the grade provided by the grader. The final grade is based on oral questions and the results of the final report.
Specific objectives	At the end of the activity the student must be able to: 1) install the microcontroller drivers. 2) load programs on the development board and run them. 3) make simple modifications to the code in c.
Links to learning outcomes	Links to learning outcomes 1, competence E21

Practice 3: traffic light implemented with finite state machine		Dedication: 4h	Large group / Theory: Directed activities: 2 Autonomous learning: 2am
General description	Implementation of a traffic light for two one-way streets with external LEDs and code in c
Support material	UVISION simulator
Deliverable and links to the evaluation	Pre-test. The final grade is based on oral questions and the results of the final report
Specific objectives	At the end of the activity the student must be able to: Connect external elements to the development board, understand the c-code of the program and simulate the traffic light
Links to learning outcomes	Links to learning outcomes 1 to 11, competence E21, E24

Practice 4: Introduction to the C language.		Dedication: 4h	Large group / Theory: Directed activities: 2 Autonomous learning: 2am
General description	Introduction to the C language. Implementation of simple calculation algorithms
Support material	UVISION simulator TM4C123G launchpad board
Deliverable and links to the evaluation	Pre-test. If so, code in c ..
Specific objectives	The final grade is based on oral questions and the results of the final report. Specific objectives At the end of the activity the student must be able to: Perform simple programs that perform simple calculations.
Links to learning outcomes	Links to learning outcomes 1,, CB3 and E21 competence

Evaluation system

Rating:

The Final Grade (NF) of the subject is obtained by weighting the Grade of Theory and Problems (NTP) and the Grade of Laboratory Practices (NL):

NF = 0.8 NTP + 0.2 NL

The subject is planned in such a way that, under normal conditions, it can be passed by continuous assessment.

Theory and Problem Note (NTP) for continuous assessment:

The NTP is obtained by weighting 3 notes (N1, ..., N3). The mark Nk (for k = 1, ..., 3) is the grade obtained in the exam Ek (which is done in the class period) as long as the student has successfully delivered 80% of the deliveries on the topics / objectives evaluated. In case of not reaching 80%, Nk will be 0.

Deliveries include both the completion on time (and at home) of the exercises and problems proposed after each theory and problem session, as well as those exercises and problems performed in the class itself.

The weights that weigh each Nk mark are proportional to the hours of work that the student dedicates to carry out the planned activities in order to achieve the evaluated objectives, as well as the relative importance of such objectives within the subject.

NTP = (N1 + N2 + N3) / 3

The Laboratory Note (NL):

The NL grade is obtained by averaging the grades of each of the 4 laboratory practices, assessed in each of the laboratory sessions. The grade for each Li laboratory practice (NLi for i = 1 ... 4) is calculated using the following formula:

NLi = 0.65 x PPi + 0.35 IFi if the full pre-login report is delivered

NLi = 0 if not delivered

On:

PPi is the mark of the individual preliminary test (about 15 minutes long), which is done at the beginning of the session and consists of questions similar to the previous practice, previous report, etc ..

IFi is the note of the final report made during the laboratory session.

Final grade:

At the end of the classes, after a few days of the E3 exam, the student will know if he has passed the subject through the continuous evaluation of theory and problems, and the evaluation of the laboratory (NF> = 5).

Recovery

Only those students who have not passed by continuous assessment and have obtained a mark of continuous assessment higher than 2,5 / 10 in the theory and problems part can take the entrance exam.

Rules for carrying out the activities

The tests will be performed individually.

The practices will be carried out in pairs or individually at the discretion of the teacher. The internship grade may be different for each group member if the teacher deems it appropriate.

It is mandatory to carry out all the activities of the subject.

REFERENCES

Basic

Internship manual [pdf].

Faúndez-Zanuy, Marcos. Internship manual [pdf]. Internal publication Tecnocampus Available on e-campus

Transparencies of the subject

Faundez-Zanuy, Marcos. Collection of transparencies of the subject [pdf]. Tecnocampus 2022 publication. Available on e-campus.

Introduction to computers

Navarro, Juan José. Introduction to computers: collection of problems and theory notes [pdf]. Internal publication UPC, 2011 Available on moodle

Complementary

Principles of digital design

Gajski, DD. Principles of digital design. Prentice Hall, 1997. ISBN 84-8322-004-0.

Quintáns Graña, Camilo "Simulation of electronic circuits with ORCAD PSPICE. 2nd Edition Editorial Marcombo 2022

101314 - DIGITAL ELECTRONICS II

Degree in Industrial and Automated Electronic Engineering

Polytechnic School

General information

Teaching languages

Skills

Specific skills

Description

Learning outcomes

Working methodology

Contents

Learning activities

Evaluation system

REFERENCES

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